Parallel status polling of multiple memory devices

摘要

An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.

主权项

1. An apparatus, comprising:
an interface, which is configured to communicate with multiple memory devices over a bus comprising a plurality of parallel data lines; and a processor, which is configured to:
assign a respective unique identifier to each of the multiple memory devices;issue a first single command to request that each memory device of a first proper subset of the multiple memory devices provides a respective status report, wherein each memory device of the first proper subset receives the first single command over all data lines of the plurality of parallel data lines of the bus during a first clock cycle of the bus;receive, in parallel, the respective status report from each memory device of the first proper subset, wherein each status report from a respective memory device of the first proper subset is received over a respective subset of the plurality data lines of the bus during a second clock cycle of the bus, and wherein the first and second clock cycles are consecutive;issue a second single command to request that each memory device of a second proper subset of the multiple memory devices provides a respective status report, wherein each memory device of the second proper subset receives the second single command over all data lines of the plurality of parallel data lines of the bus during a third clock cycle of the bus, and wherein the first proper subset and the second proper subset are different; andreceive, in parallel, the respective status report from each memory device of the second proper subset, wherein each status report from a respective memory device of the second proper subset of the multiple memory devices is received over a respective subset of the plurality data lines of the bus during a fourth clock cycle of the bus, and wherein the third and fourth clock cycles are consecutive.