| 摘要 |
FIELD: computer engineering.SUBSTANCE: invention relates to computer engineering. Processor configured for selection of commands from instruction cache, each command sets particular access to memory; decoding each of commands to generate decoded commands; evaluation of decoded instructions using criteria binding operations in memory to selectively identify possibility of binding operations in memory in a plan of access to memory associated with decoded instructions; and creation of combined operations in memory in accordance with possibilities of binding operations in memory in order to generate corrected memory access plan with accelerated access to memory, corrected plan memory access includes one command, which combines multiple private decoded commands and sets balanced address.EFFECT: technical result is optimisation of operations in memory.20 cl, 1 dwg |
