发明名称 Shared memory controller and method of using same
摘要 Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses. The method further includes concurrently dispatching the respective sequences of beat-level read/write commands to the shared memory, thereby accessing the shared memory.
申请公布号 US9335934(B2) 申请公布日期 2016.05.10
申请号 US201414265127 申请日期 2014.04.29
申请人 Futurewei Technologies, Inc. 发明人 Luan Hao;Gatherer Alan;Bei Yan;Ying Jun
分类号 G06F12/00;G06F3/00;G06F3/06 主分类号 G06F12/00
代理机构 Slater Matsil, LLP 代理人 Slater Matsil, LLP
主权项 1. A method for controlling access to a shared memory, comprising: concurrently scanning-in a plurality of read/write commands for respective transactions, wherein each of the plurality of read/write commands includes respective addresses and respective priorities, wherein each of the respective transactions is divisible into at least one beat, and wherein at least one of the respective transactions is divisible into multiple beats; dividing the plurality of read/write commands into respective beat-level read/write commands; generating respective sequences of beat-level read/write commands corresponding to the respective addresses with concurrent arbitrating of the respective beat-level read/write commands according to the respective addresses and the respective priorities; and concurrently dispatching the respective sequences of beat-level read/write commands to the shared memory.
地址 Plano TX US