Adaptively controlling low power mode operation for a cache memory

摘要

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a plurality of cores each to independently execute instructions; a cache memory including a plurality of portions distributed across a die of the processor; a plurality of sleep circuits each coupled to one of the plurality of portions of the cache memory; and at least one sleep control logic coupled to the plurality of portions of the cache memory to dynamically determine a sleep setting independently for each of the plurality of sleep circuits based at least in part on a process, voltage, and temperature associated with the corresponding portion of the cache memory and dynamically determine a retention voltage for the corresponding portion of the cache memory based at least in part on the sleep setting, wherein the at least one sleep control logic is to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at the retention voltage.