发明名称 |
Manufacturing method of wafer level chip scale package structure |
摘要 |
A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion. |
申请公布号 |
US9337049(B1) |
申请公布日期 |
2016.05.10 |
申请号 |
US201514694256 |
申请日期 |
2015.04.23 |
申请人 |
NIKO SEMICONDUCTOR CO., LTD.;SUPER GROUP SEMICONDUCTOR CO., LTD. |
发明人 |
Hsieh Chih Cheng;Hsu Hsiu Wen |
分类号 |
H01L21/56;H01L21/304;H01L21/306;H01L21/78;H01L29/78;H01L21/768;H01L21/48 |
主分类号 |
H01L21/56 |
代理机构 |
Li & Cai Intellectual Property (USA) Office |
代理人 |
Li & Cai Intellectual Property (USA) Office |
主权项 |
1. A manufacturing method of a wafer level chip scale package structure comprising:
providing a wafer having a plurality of semiconductor devices, wherein a first semiconductor device of the semiconductor devices has an active surface and a back surface, the active surface has an active region and an outer region, a first electrode and a second electrode are arranged in the active region, and the outer region is divided into a cutting portion and a channel portion; forming an patterned protecting layer on the active surface, wherein the patterned protecting layer has a plurality of openings to respectively expose the first electrode, the second electrode, and the channel portion; performing a thinning process from the back surface; forming a back electrode layer on the back surface; performing an etching process to form a trench exposing the back electrode layer at the channel portion; forming a conductive structure through the trench to connect the back electrode layer; and performing a cutting process along the cutting portion. |
地址 |
New Taipei TW |