CMOS input buffer circuit

摘要

A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

主权项

1. A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit, comprising a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance; wherein
the CMOS input follower circuit, for following changes of input signals and outputting follower input signals; the linearity improvement circuit of follower transistor, for obtaining changes of input signals and giving feedback to CMOS input follower circuit; the current source load, for providing a bias current for CMOS input follower circuit; the linearity improvement circuit of load impedance, being placed between CMOS input follower circuit and current source load, for enhancing absolute load impedance of current source, restraining its fluctuation and improving load impedance linearity of CMOS input buffer.