Pipeline register with data alignment therein

摘要

A device is disclosed that includes a first memory module and a second memory module. The first memory module is configured to output a data signal according to a first phase of a first control signal. The second memory module is connected to the first memory module and includes a latch and a derace latch. The latch is configured to hold a received data signal according to a second phase of a second control signal. The derace latch transmits the data signal from the first memory module to the latch according to the second phase of both of the first control signal and the second control signal.

主权项

1. A device, comprising:
a first memory module configured to output a data signal according to a first phase of a first control signal; and a second memory module connected to the first memory module and comprising:
a latch configured to hold a received data signal according to a second phase of a second control signal; anda derace latch configured to transmit the data signal from the first memory module to the latch according to the second phase of both of the first control signal and the second control signal.