Memory error detection circuitry

摘要

Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.

主权项

1. A method of generating a parity check matrix used for error detection, wherein the parity check matrix includes logic high and logic low bits arranged in rows and columns, the method comprising:
providing a Boolean formula that defines a set of constraints, wherein the set of constraints determines an upper bound on the number of logic high bits are in each column, whether certain types of errors are detectable, and whether the detectable errors are correctable; and generating the parity check matrix by solving the set of constraints using a Boolean equation solver running on computing equipment.