Variable resistance nonvolatile memory device including a variable resistance layer that changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal

摘要

A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.

主权项

1. A variable resistance nonvolatile memory device comprising:
a nonvolatile memory element that includes a first electrode, a second electrode, and a variable resistance layer between the first electrode and the second electrode, and that changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal; an NMOS transistor including a first diffusion layer region, a gate, and a second diffusion layer region, the first diffusion layer region being connected to the first electrode; a source line connected to the second diffusion layer region; a bit line connected to the second electrode; a source line drive circuit that is connected to the source line and that includes i) a current steering circuit connected to a first voltage source, ii) a first switch circuit disposed between the source line and an output of the current steering circuit, iii) a second switch circuit disposed in parallel with the first switch between the source line and a reference potential point; a bit line drive circuit that is connected to the bit line and that includes i) a third switch circuit disposed between the bit line and the reference potential point, and ii) a fourth switch circuit disposed in parallel with the third switch between the bit line and a second voltage source; and a control circuit that controls at least the NMOS transistor, the source line drive circuit and the bit line drive circuit, wherein the nonvolatile memory element completes to change from the high resistance state to the low resistance state when a voltage higher than or equal to a low resistance change ending voltage is applied between the first electrode and the second electrode, wherein the low resistance change ending voltage varies in a range between a first voltage and a second voltage higher than the first voltage, and wherein when the control circuit causes the nonvolatile memory element to be in the low resistance state for a writing operation, i) the control circuit turns on the first switch circuit and the third switch circuit, and turns off the second switch circuit and the fourth switch circuit to flow a first current from the first voltage source to the reference potential point, and ii) the control circuit applies a first gate voltage to the gate of the NMOS transistor, and wherein when the control circuit causes the nonvolatile memory element to be in the high resistance state for the writing operation, i) the control circuit turns off the first switch circuit and the third switch circuit, and turns on the second switch circuit and the fourth switch circuit to flow a second current from the second voltage source to the reference potential point, and ii) the control circuit applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.