Recycling error bits in floating point units

摘要

A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.

主权项

1. A system, comprising:
a memory; and a processing device communicably coupled to the memory, the processing device comprising a floating point unit (FPU) to:
generate a result value from applying an operation on floating point number inputs to the FPU;generate an error value using the result value, wherein the error value is the difference between a rounded result produced by the FPU and a result obtained with an infinite-precision FPU;write the result value to a first register of the processing device dedicated to storing results from the operation of the FPU; andwrite the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.