Generalized parallel counter structures in logic devices

摘要

Generalized parallel counter circuitry is configured from logic elements—e.g., on a programmable integrated circuit device. Each logic element includes a logic stage, an adder and an output stage. The logic stage includes logic units, and a logic stage selector for selectively outputting to an input of the adder at least one of (a) outputs of the logic units, and (b) a first logic unit output of another one of the logic elements, and for selectively outputting to the output stage one of (a) an output of the logic units, and (b) a first output of the adder. The output stage includes at least two outputs, an output selector for selectively outputting, to the at least two outputs, at least one of (a) a second output of the adder, and (b) an output of the logic stage selector.

主权项

1. A logic element for a programmable integrated circuit device, said logic element comprising:
a logic stage; an adder; and an output stage; wherein said logic stage comprises: logic units, a first logic stage selector having as inputs (a) a first output of said logic units, and (b) a first logic unit output of another said logic element, said first logic stage selector selectably outputting to an input of said adder at least (a) said first output of said logic units, or (b) said first logic unit output of said another said logic element, and a second logic stage selector having as inputs (a) a second output of said logic units, and (b) an output of said adder, said second logic stage selector selectably outputting to said output stage (a) said second output of said logic units, or (b) said output of said adder.