发明名称 Method for fabricating active matrix substrate and method for fabricating display device
摘要 A gate line is formed on a pixel region, and a plurality of wiring layers are formed on a frame region. Next, a gate insulating layer and a semiconductor material layer are formed to cover the wiring layers and the gate line. Next, a first resist is formed to cover a portion of the semiconductor material layer over the pixel region, and second resists are formed to individually cover portions of the gate insulating layer between adjacent pairs of the wiring layers. Next, portions of the semiconductor material layer exposed from the first and second resists and are etched by dry etching to form semiconductor layers of semiconductor elements.
申请公布号 US9337215(B2) 申请公布日期 2016.05.10
申请号 US201314401158 申请日期 2013.06.17
申请人 Sharp Kabushiki Kaisha 发明人 Inoue Tsuyoshi
分类号 H01L21/027;H01L27/12;G02F1/1362;H01L21/768 主分类号 H01L21/027
代理机构 Keating & Bennett, LLP 代理人 Keating & Bennett, LLP
主权项 1. A method for fabricating an active matrix substrate, the method comprising: forming, on a pixel region of the active matrix substrate, a gate line forming portions of a plurality of semiconductor elements, and forming a plurality of wiring layers on a frame region of the active matrix substrate surrounding the pixel region, the wiring layers being made of a same material as the gate line and extending in parallel; forming a gate insulating layer on the frame region and the pixel region to cover the wiring layers and the gate line; forming a semiconductor material layer on a surface of the gate insulating layer on the frame region and the pixel region; forming a first resist covering a portion of the semiconductor material layer over the pixel region, and second resists individually covering portions of the gate insulating layer between adjacent pairs of the wiring layers; and etching portions of the semiconductor material layer exposed from the first and second resists by dry etching to form semiconductor layers forming portions of the semiconductor elements; wherein in the forming of the second resists, only portions of each of the adjacent pairs of the wiring layers are covered by each of the second resists with remaining portions of the adjacent pairs remaining uncovered by the second resists.
地址 Osaka JP