| 发明名称 | Semiconductor memory apparatus | ||
| 摘要 | A semiconductor memory apparatus may include an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal. The semiconductor memory apparatus may also include a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled. | ||
| 申请公布号 | US9336854(B2) | 申请公布日期 | 2016.05.10 |
| 申请号 | US201414505140 | 申请日期 | 2014.10.02 |
| 申请人 | SK hynix Inc. | 发明人 | Ko Jae Bum |
| 分类号 | G11C8/08;G11C11/406;G11C11/4093 | 主分类号 | G11C8/08 |
| 代理机构 | William Park & Associates Ltd. | 代理人 | William Park & Associates Ltd. |
| 主权项 | 1. A semiconductor memory apparatus comprising: an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal; and a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled. | ||
| 地址 | Icheon-si Gyeonggi-do KR | ||