Driving circuit for voice coil motor, lens module and electronic device using the same, and driving method for voice coil motor

摘要

A driving circuit for controlling a driving current is provided. A D/A converter has a precision of N bits and outputs a control signal for a driving current to a current driver. A logic unit receives input control data of M bits (M>N) and outputs intermediate control data of N bits to the D/A converter. A data extraction unit divides the input control data into a first data having N bits from the MSB and a second data having (M−N) bits from the LSB. A counter accumulatively adds the second data to generate a count. A carry detection unit asserts a carry signal when a carry at the MSB of the count is generated by the counter. An output control unit 66 converts the intermediate control data into the first data or a third data, in which 1 LSB is added to the first data, according to the carry signal.

主权项

1. A driving circuit configured to supply a driving current to a voice coil motor, the driving circuit comprising:
a D/A converter of a second number (N) of bits, wherein the second number (N) is an integer; a current driver configured to generate the driving current based on a control signal outputted from the D/A converter; and a logic unit configured to receive an input control data having a first number (M) of bits and output an intermediate control data having the second number (N) of bits to the D/A converter, wherein the first number (M) is an integer larger than the second number (N), and wherein the logic unit comprises:
a data extraction unit configured to divide the input control data into a first data having the second number (N) of bits from a most significant bit of the input control data and a second data having a third number (M−N) of bits from a least significant bit of the input control data , wherein the third number (M−N) corresponds to a number from subtracting the second number (N) from the first number (M);a counter configured to accumulatively add the second data in synchronization with a clock signal to generate a count value having the third number (M−N) of bits;a carry detection unit configured to assert a carry signal when a carry at a most significant bit of the count value is generated by the counter; andan output control unit configured to set the intermediate control data as the first data in a cycle where the carry signal is negated or set the intermediate control data as a third data, in which one least significant bit is added to the first data, in a cycle where the carry signal is asserted.