| 主权项 |
1. A method of forming a barrier in a vertical field effect transistor with low effective mass channel materials, comprising:
forming a first source/drain contact on a semiconductor substrate; forming a channel with a first channel layer on the first source/drain contact, a barrier on the first channel layer, and a second channel layer on the barrier; forming a second source/drain contact on the second channel layer; patterning a first dielectric layer and the second source/drain contact on the second channel layer to form a first pillar; forming a first spacer on the second channel layer, the first spacer surrounding the second source/drain contact and the first dielectric layer; patterning the second channel layer, the barrier, and the first channel layer to form a second pillar, the second pillar including the first spacer, the second source/drain contact, and the first dielectric layer; depositing a gate dielectric layer covered by a gate electrode layer over a portion of the semiconductor substrate, a portion of the first source/drain contact, around the second pillar, and over the second pillar; forming a second spacer; forming a gate electrode from the gate electrode layer; forming a third spacer adjacent to the second pillar on the gate dielectric layer, the gate dielectric layer being on a portion of the first source/drain contact; depositing an interlayer dielectric layer over the gate dielectric layer and adjacent to the third spacer; and depositing a contact metal to form metal contacts by selectively removing the first dielectric layer, the second spacer, a portion of the interlayer dielectric layer, and a portion of the gate dielectric layer under the removed portion of the interlayer dielectric layer. |
