Data processing apparatus and method for use in an interleaver suitable for multiple operating modes

摘要

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

主权项

1. A data processing apparatus, comprising:
a linear feedback shift register configured to output a pseudo-random first value; toggle circuitry configured to generate and to add one bit to the first value to form a second value; address generation circuitry configured to add an offset to the second value to form an address having a third value; and mapping circuitry configured to map a data cell onto one of a plurality of sub-carrier signals identified by said address.