发明名称 Method and system for smart card chip personalization
摘要 Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.
申请公布号 US9338004(B2) 申请公布日期 2016.05.10
申请号 US201314432426 申请日期 2013.10.08
申请人 NAGRAVISION S.A. 发明人 Hautier Roan;Macchetti Marco;Perrine Jerome
分类号 H04L9/00;H04L9/08;G06F21/57;G06F21/76;G06F21/31;G06F21/44;H04L9/14 主分类号 H04L9/00
代理机构 DLA Piper LLP US 代理人 DLA Piper LLP US
主权项 1. A method for personalizing at least one chip, intended to be integrated into a smart card, comprising: sending by a tester a first secret code to a Field Programmable Gate Array (FPGA) device connected to the at least one chip, the at least one chip being part of a wafer comprising an arrangement of a plurality of chips, the tester being associated to the FPGA device, said first secret code being stored permanently in a memory of the tester; sending by the FPGA device a command to the at least one chip to initiate a sequence of a test mode activation; sending by the at least one chip a signal to a disposable hardware module arranged on the wafer and receiving from, said disposable hardware module a response indicating presence of the at least one chip on the wafer; generating and sending by the at least one chip a random number to the FPGA device; encrypting by the FPGA device a second secret code by using a secret encryption algorithm parameterized with the random number and the first secret code, to obtain a first cryptogram; sending by the FPGA device the first cryptogram, to the at least one chip; determining by the at least one chip a second cryptogram by carrying out a Boolean function over a result obtained by decrypting the first cryptogram using the inverse of the secret encryption algorithm parameterized with the random number and the first secret code; comparing by the at least one chip the second cryptogram with a result obtained by carrying the Boolean function over the second secret code temporarily stored on the at least one chip; if the second cryptogram corresponds to the result obtained by carrying out the Boolean function over the second secret code, enabling the test mode activation; sending by the at least one chip a response message to the FPGA device; and performing, by the FPGA device, personalization of the at least one chip if the response message includes a positive response, wherein personalization comprises storing unique secret data on the at least one chip.
地址 Cheseaux-sur-Lausanne CH