Tucked active region without dummy poly for performance boost and variation reduction

摘要

In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

主权项

1. A method of forming a semiconductor device comprising:
providing a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region; forming at least one functional gate structure on a portion of the active region that is separated from the at least one trench isolation region; forming an interface replacement gate structure on an interface between the active region of the semiconductor substrate and the at least one trench isolation region, wherein the interface replacement gate structure includes a gate stack of a sacrificial gate conductor structure and a gate dielectric, and a spacer adjacent to the gate stack; forming embedded semiconductor regions in the active region of the semiconductor substrate between the portion of the active region that the functional gate structure is present on and the portion of the active region at the interface with the at least one trench isolation region that the replacement gate structure is present on; forming source regions and drain regions on opposing sides of the portion of the semiconductor substrate that the functional gate structure is formed on; and removing at least a portion of the interface replacement gate structure such that the sacrificial gate conductor structure and the spacer of the interface replacement gate structure are removed, while the gate dielectric of the interface replacement gate structure remains.