发明名称 Hybrid linear validation algorithm for software transactional memory (STM) systems
摘要 A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.
申请公布号 US9336066(B2) 申请公布日期 2016.05.10
申请号 US200812142097 申请日期 2008.06.19
申请人 Intel Corporation 发明人 Welc Adam;Saha Bratin;Adl-Tabatabai Ali-Reza
分类号 G06F9/52;G06F9/46 主分类号 G06F9/52
代理机构 Barnes & Thornburg LLP 代理人 Barnes & Thornburg LLP
主权项 1. A non-transitory, machine readable medium including program code stored thereon which, when executed, causes a machine to perform the operations of: determining a data element has been read by and written to by a transaction; updating a meta-data location associated with the data element from a direct reference to a transaction descriptor associated with the transaction to a direct reference to a write entry associated with the data element in response to determining the data element has been read by and written to by the transaction, wherein updating the meta-data location comprises replacing the direct reference to the transaction descriptor with the direct reference to the write entry; and updating the meta-data location to a version value upon committing the transaction after updating the meta-data location associated with the data element from the reference to the transaction descriptor to the reference to the write entry in response to determining the data element is read by and written to by the transaction.
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