Shared function multi-ported ROM apparatus and method

摘要

Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.

主权项

1. An apparatus comprising:
an execution unit comprising a logic circuit, the logic circuit operative to execute:
a first array of functions comprised of a first set of single instruction, multiple data (SIMD) operations; anda second array of functions comprised of a second set of SIMD operations; and multiple ports communicatively coupled with the logic circuit, each of the multiple ports comprising a plurality of wordlines operative to supply data to the logic circuit, a first one of the plurality of wordlines of each of the multiple ports to share the logic circuit to access the first array of functions and a second one of the plurality of wordlines of each of the multiple ports to share the logic circuit to access the second array of functions.