| 摘要 |
A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by 1/4 of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of, since the phase difference of the delayed lower sideband analog signal and the upper sideband analog signal is aligned at 180 degrees, latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal, that is, a BPSK modulation signal, generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator. |
