| 摘要 |
Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature. |
