发明名称 3D NVM AND DRAM MEMORY DEVICE
摘要 A memory system able to store information using a hybrid volatile and nonvolatile memory device organized in a stacking configuration is disclosed. The memory system, in one aspect, includes memory components, a drain select gate ("DSG") transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory ("DRAM") function.
申请公布号 WO2016069487(A1) 申请公布日期 2016.05.06
申请号 WO2015US57403 申请日期 2015.10.26
申请人 NEO SEMICONDUCTOR INC. 发明人 HSU, FU-CHANG
分类号 G11C7/10;H01L21/30;H01L23/48 主分类号 G11C7/10
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