发明名称 3D MEMORY WITH ERROR CHECKING AND CORRECTION FUNCTION
摘要 An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.
申请公布号 US2016124810(A1) 申请公布日期 2016.05.05
申请号 US201514928317 申请日期 2015.10.30
申请人 RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY 发明人 YANG Joon-sung;HAN Hyunseung
分类号 G06F11/10;G11C29/52 主分类号 G06F11/10
代理机构 代理人
主权项 1. An error check and correction method of a 3D memory, in which a plurality of memory layers are stacked, the method comprising: a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.
地址 Suwon-si KR