发明名称 |
LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON |
摘要 |
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions. |
申请公布号 |
US2016126094(A1) |
申请公布日期 |
2016.05.05 |
申请号 |
US201414534131 |
申请日期 |
2014.11.05 |
申请人 |
International Business Machines Corporation |
发明人 |
Fogel Keith E.;Hashemi Pouya;Khakifirooz Ali;Reznicek Alexander |
分类号 |
H01L21/02;H01L29/06;H01L29/20 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Armonk NY US |