SEMICONDUCTOR STORAGE DEVICE

摘要

There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode.

主权项

1. A semiconductor storage device comprising:
a memory array comprising a plurality of memory cells provided in rows and columns; and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements, the control circuit comprising: a first switching transistor provided between a source line and a first voltage, the source line being coupled to a source electrode of the driving transistors; a second switching transistor provided in parallel with the first switching transistor between the source line and the first voltage; and a source line potential control circuit that adjusts the potential of the source line by controlling the first and second switching transistors, wherein, the source line potential control circuit makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line, when the memory cells are in standby mode.