TFT SUBSTRATE WITH VARIABLE DIELECTRIC THICKNESS

摘要

A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness.

主权项

1. A transistor comprising:
a substrate; an electrically conductive gate over the substrate, the gate having a gate length; a source electrode and a drain electrode over the substrate, the source and drain electrodes separated by a gap defining a channel region, the channel region having a channel length that is less than the gate length; a semiconductor layer in contact with the source and drain electrodes, the semiconductor layer having a semiconductor pattern; a dielectric stack having a portion in contact with the gate having first, second, and third regions, the first region in contact with the semiconductor layer in the channel region and having a first thickness, the second region adjacent to the first region and having the first thickness, and the third region adjacent to the second region and having a thickness that is greater than the first thickness, wherein the dielectric stack includes a plurality of layers with one of the plurality of layers that is in contact with the semiconductor layer having a different pattern than another of the plurality of layers, the layer of the dielectric stack that is in contact with the semiconductor layer having the same semiconductor pattern, and the layer of the dielectric stack that is in contact with the semiconductor layer having terminating edges that are aligned to be coincident with corresponding terminating edges of the semiconductor layer.