THERMAL TREATED SEMICONDUCTOR/GATE DIELECTRIC INTERFACE FOR GROUP IIIA-N DEVICES

摘要

A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.

主权项

1. A method of fabricating a gate stack for a power transistor device, comprising:
thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer comprising an oxide material that is >5 A thick; depositing a second dielectric layer comprising silicon nitride or silicon oxynitride on said first dielectric layer, and forming a metal gate electrode on said second dielectric layer.