发明名称 MEMORY BUS ERROR SIGNAL
摘要 A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.
申请公布号 EP3014449(A1) 申请公布日期 2016.05.04
申请号 EP20130888427 申请日期 2013.06.27
申请人 HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP 发明人 BENEDICT, MELVIN K.
分类号 G06F11/08;G06F13/14;G06F13/16 主分类号 G06F11/08
代理机构 代理人
主权项
地址