| 摘要 |
A device for converting a signal into a pulse width modulated (PWM) signal comprises one or more add/subtract units 104 receiving both input and decimated signals and outputting a compensated signal having a first sampling frequency, an interpolation filter 108 for generating an interpolated signal and a pulse-width modulator 110 clocked at a second, higher sampling frequency for generating a PWM signal from received interpolation and carrier signals. A decimation filter 114 within a noise-shaping loop 112 receives the PWM signal and outputs a representative decimated signal at the first frequency. The interpolator may comprise a sample-and-hold device and may be clocked at the first frequency. Logic circuitry 116 may be coupled to both interpolator and decimator and may determine whether the interpolated and carrier signals will intersect in a next clock period of the sample-and-hold device, or a phase of the intersection, and control the decimator to output a value in response. The phase of the intersection may be expressed as an integer number of clock cycles of the second frequency. The decimator may comprise a low-pass filter, sampler and look-up table with stored step responses, and may be clocked at the first frequency. |
