A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.
申请公布号
EP2843550(A3)
申请公布日期
2016.05.04
申请号
EP20140179294
申请日期
2014.07.31
申请人
VIA TECHNOLOGIES, INC.
发明人
HENRY, G. GLENN;PARKS, TERRY;GASKINS, DARIUS D.;GASKINS, STEPHAN;HOOKER, RODNEY E.;BEAN, BRENT