发明名称 Flip chip bump array with superior signal performance
摘要 An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.
申请公布号 US9332629(B2) 申请公布日期 2016.05.03
申请号 US201012938196 申请日期 2010.11.02
申请人 INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 Shah Jitesh
分类号 H01L23/488;H05K1/11;H05K1/02;H01L23/50;H01L23/528;H01L23/498;H05K3/34 主分类号 H01L23/488
代理机构 Roeder & Broder LLP 代理人 Roeder & Broder LLP
主权项 1. A circuit assembly comprising: a printed circuit board; a package substrate electrically connected to the printed circuit board, the package substrate including a package body; and a pin array that electrically connects the package body to the integrated circuit, the pin array including (i) a first pin set that is rectangular tube shaped and includes a plurality of signal pins and a plurality of non-signal pins that are alternatingly interspersed around the rectangular tube shaped first pin set; and (ii) a second pin set that is rectangular tube shaped and that encircles the first pin set, wherein the second pin set includes a plurality of signal pins and a plurality of non-signal pins that are alternatingly interspersed around the rectangular tube shaped second pin set; wherein each non-signal pin is either a ground pin or a power pin; and wherein each pin set includes four corner pins, and wherein each corner pin of each pin set is a signal pin; and an integrated circuit including a circuit body; and a bump array that is electrically connected to the pin array of the package substrate, the bump array including (i) a first bump set that is rectangular tube shaped and includes a plurality of signal bumps and a plurality of non-signal bumps that are alternatingly interspersed around the rectangular tube shaped first bump set; and (ii) a second bump set that is rectangular tube shaped and that encircles the first bump set, wherein the second bump set includes a plurality of signal bumps and a plurality of non-signal bumps that are alternatingly interspersed around the rectangular tube shaped second bump set; wherein each non-signal bump is either a ground bump or a power bump; and wherein each bump set includes four corner bumps, and wherein each corner bump of each bump set is a signal bump.
地址 San Jose CA US