发明名称 |
Methods and structures for forming microstrip transmission lines on thin silicon on insulator (SOI) wafers |
摘要 |
A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line. |
申请公布号 |
US9331153(B2) |
申请公布日期 |
2016.05.03 |
申请号 |
US201314105497 |
申请日期 |
2013.12.13 |
申请人 |
RAYTHEON COMPANY |
发明人 |
LaRoche Jeffrey R. |
分类号 |
H01L29/20;H01L21/02;H01L21/762;H01L21/768;H01L21/8258;H01L23/66;H01L21/683 |
主分类号 |
H01L29/20 |
代理机构 |
Daly, Crowley, Mofford & Durkee, LLP |
代理人 |
Daly, Crowley, Mofford & Durkee, LLP |
主权项 |
1. A structure, comprising:
a first silicon layer; a first insulating layer disposed under the first silicon layer; a second insulating layer; a second silicon layer, disposed under the second insulating layer; wherein the first insulating layer is directly bonded to the second insulating layer; wherein the second silicon layer is thicker than the first silicon layer; and wherein the second silicon layer is more heavily doped than the first silicon layer and wherein the first silicon layer has a <111> crystallographic orientation and the second silicon layer has a <100> crystallographic orientation. |
地址 |
Waltham MA US |