发明名称 Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
摘要 Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
申请公布号 US9331092(B2) 申请公布日期 2016.05.03
申请号 US201514706130 申请日期 2015.05.07
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 Yater Jane A.;Hong Cheong Min;Kang Sung-Taeg
分类号 H01L29/788;H01L27/115;H01L29/423 主分类号 H01L29/788
代理机构 代理人
主权项 1. A split-gate non-volatile memory (NVM) cell array, comprising: select gate structures for a plurality of split-gate NVM cells within the split-gate NVM cell array formed using a first material layer; dummy select gate structures also formed using the first material layer; control gate structures for the plurality of split-gate NVM cells formed using a second material layer and a non-patterned spacer etch; charge storage layers for the plurality of split-gate NVM cells associated with the select gate structures and the control gate structures; contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and electrical contacts coupled to the contact landing regions; wherein each of the plurality of split-gate NVM cells comprises one of the charge storage layers formed between one of the select gate structures and one of the control gate structures.
地址 Austin TX US