Single power supply level shifter

摘要

A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.

主权项

1. A single power supply level shifter for a semiconductor device having first and second power supply voltage domains, the level shifter comprising:
a first inverter inverting an input signal from the first voltage domain and providing a first inverted signal in the second voltage domain; a second inverter inverting the first inverted signal and providing an output signal in the second voltage domain; a capacitor element; a charging control circuit charging the capacitor element towards the second voltage when the input signal is high, and conducting a discharge current from the capacitor element during a transition of the input signal from high to low, wherein the discharge current accelerates a corresponding transition of the first inverted signal from low to high; a current reduction module having a current conduction path of a current reduction transistor connected in series with a current conduction path of the first inverter; and a third inverter providing a third inverted signal in the second voltage domain to a control electrode of the current reduction transistor to reduce the current in the current reduction transistor and the first inverter when the first inverted signal is low, wherein the charging control circuit charges the capacitor from the third inverted signal when the input signal is high.