发明名称 Memory cell array and variable resistive memory device including the same
摘要 A memory cell array includes a semiconductor substrate, a first word line formed on the semiconductor substrate, a second word line formed on the semiconductor substrate and extending substantially parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, first active pillars formed within the first word line and arranged along the first word line at a first interval, and second active pillars formed within the second word lines, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween.
申请公布号 US9331273(B2) 申请公布日期 2016.05.03
申请号 US201414328382 申请日期 2014.07.10
申请人 SK Hynix Inc. 发明人 Kim Sung Cheoul;Choi Kang Sik
分类号 H01L29/02;H01L29/76;H01L29/788;H01L21/8239;H01L45/00;H01L27/24 主分类号 H01L29/02
代理机构 IP & T Group LLP 代理人 IP & T Group LLP
主权项 1. A memory cell array, comprising: a semiconductor substrate; a first word line formed on the semiconductor substrate; a second word line formed on the semiconductor substrate, and extending substantially parallel to the first word line; a first inter-pattern insulating layer interposed between the first and second word lines; first active pillars formed within the first word line, and arranged along the first word line at a first interval; and second active pillars formed within the second word line, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween, wherein one side of each first active pillar is in contact with one side of the first inter-pattern insulating layer and one side of each second active pillar is in contact with the other side of the first inter-pattern insulating layer.
地址 Gyeonggi-do KR