Package carrier and manufacturing method thereof

摘要

A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided. A portion of the upper surface is exposed by the patterned circuit layer. An insulating layer and a conducting layer located at a first surface of the insulating layer are laminated onto the patterned circuit layer. The patterned circuit layer and the exposed portion of the upper surface are covered by the insulating layer. Plural conductive connection structures are formed on the patterned circuit layer. Plural of pads respectively connecting the conductive connection structures and exposing a portion of the first surface of the insulating layer is defined by patterning the conductive layer. The supporting board is removed so as to expose a second surface of the insulating layer. The second surface and a bonding surface of the patterned circuit layer are coplanar.

主权项

1. A manufacturing method of a package carrier, comprising:
providing a supporting board having an upper surface; forming a patterned circuit layer directly on the upper surface of the supporting board, wherein the patterned circuit layer exposes a portion of the upper surface of the supporting board, and the patterned circuit layer comprises at least one die pad; laminating an insulating layer and a conductive layer located at a first surface of the insulating layer directly onto the patterned circuit layer, wherein the insulating layer covers the patterned circuit layer and the portion of the upper surface of the supporting board exposed by the patterned circuit layer; forming a plurality of conductive connection structures directly on the patterned circuit layer; patterning the conductive layer to define a plurality of pads respectively connected to the conductive connection structures and to expose a portion of the first surface of the insulating layer; removing the supporting board to expose a second surface opposite to the first surface of the insulating layer, wherein the second surface of the insulating layer and a bonding surface of the patterned circuit layer are coplanar; forming a solder resist layer directly on the second surface of the insulating layer after removing the supporting board, wherein a portion of the bonding surface of the patterned circuit layer is exposed by the solder resist layer; and forming a surface treatment layer directly on the bonding surface of the patterned circuit layer after removing the supporting board, wherein a portion of the surface treatment layer is located between a chip and the die pad, a height difference is between a first top surface of the solder resist layer and a second top surface of the surface treatment layer so as to form a cavity between a sidewall of the solder resist layer and the second top surface of the surface treatment layer, and portions of the chip is embedded in the cavity formed by the solder resist layer and surface treatment layer, and a bottom surface of the chip is lower than the first top surface of the solder resist layer.