| 主权项 |
1. A clock and data recovery circuit, comprising:
a phase detector, configured to detect a phase difference between an input signal and a clock signal to output at least one first phase signal; an inversing circuit, coupled to the phase detector, and configured to output at least one second phase signal according to the at least one first phase signal and a test mode signal; a filter circuit, coupled to the inversing circuit, and configured to filter the at least one second phase signal to generate a digital control signal; a digital control oscillator, coupled to the filter circuit, and configured to generate the clock signal according to the digital control signal; a decision circuit, configured to sample the input signal according to the clock signal to obtain a data signal; and a computing circuit, coupled to the decision circuit, and configured to determine whether the data signal has an error, wherein when the test mode signal indicates an operation mode, the inversing circuit set the at least one second phase signal to be identical to the at least one first phase signal, wherein when the test mode signal indicates a test mode, the computing circuit starts counting, and the inversing circuit inverses the at least one first phase signal to generate the at least one second phase signal, wherein when determining that the data signal has the error during the test mode, the computing circuit stops counting to generate at least one count value, and computes at least one tracing speed according to the at least one count value and a predetermined unit interval, and wherein the filter circuit comprises a proportional gain amplifier and an integral gain amplifier, the inversing circuit enables the proportional gain amplifier and disables the integral gain amplifier during a first time period of the test mode, and the inversing circuit disables the proportional gain amplifier and enables the integral gain amplifier during a second time period of the test mode. |
