发明名称 Frequency shift keying transmitter
摘要 According to embodiments of the present invention, a frequency shift keying transmitter is provided. The frequency shift keying transmitter includes a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement, a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal, and a sampling arrangement coupled to the logic gate arrangement, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement is configured to be controlled by the data signal to have the logic gate arrangement select periodic waveforms that are delayed from each other by one of a set of intervals associated with the data signal, to be used as the input signals to the logic gate arrangement to produce the output signal.
申请公布号 US9331878(B2) 申请公布日期 2016.05.03
申请号 US201214125456 申请日期 2012.06.14
申请人 Agency for Science, Technology and Research 发明人 Cheng San Jeow;Gao Yuan;Zheng Yuanjin;Heng Chun Huat
分类号 H04B7/02;H04L1/02;H04L27/12;H04L27/156 主分类号 H04B7/02
代理机构 Crockett & Crockett, PC 代理人 Crockett, Esq. K. David;Syrengelas, Esq. Niky Economy;Crockett & Crockett, PC
主权项 1. A frequency shift keying transmitter comprising: a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement; a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal; and a sampling arrangement coupled to the logic gate arrangement, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement is configured to be controlled by the data signal to have the logic gate arrangement select periodic waveforms that are delayed from each other by one of a set of intervals associated with the data signal, to be used as the input signals to the logic gate arrangement to produce the output signal, wherein the selected periodic waveforms are merged to produce the output signal, wherein the sampling arrangement comprises a delta-sigma modulator coupled to a frequency interpolator, the delta-sigma modulator configured to receive the data signal and providing sampling data to the frequency interpolator, the frequency interpolator configured to produce the input signal byFinf=1Tclk-(K2m×Tclk12)⁢⁢for⁢⁢0≤K≤2mwhere K and m are the input control word and the input bit resolution of the delta-sigma modulator respectively, and Tclk is an average clock period related to the input control word K; and wherein the output signal is a frequency shift keying signal.
地址 Singapore SG