Semiconductor light emitting device, including a plurality of barrier layers and a plurality of well layers, and method for manufacturing the same

摘要

According to one embodiment, a semiconductor light emitting device includes first and second semiconductor layers, and a light emitting unit. The light emitting unit is provided between the first and second semiconductor layers and includes well layers and barrier layers. The barrier layers include p-side and n-side barrier layers, and a first intermediate barrier layer. The n-side barrier layer is provided between the p-side barrier layer and the first semiconductor layer. The first intermediate barrier layer is provided between the barrier layers. The well layers include p-side and n-side well layers, and a first intermediate well layer. The p-side well layer is provided between the p-side barrier layer and the second semiconductor layer. The n-side well layer is provided between the n-side barrier layer and the first intermediate barrier layer. The first intermediate well layer is provided between the first intermediate barrier layer and the p-side barrier layer.

主权项

1. A semiconductor light emitting device, comprising:
a first semiconductor layer including a nitride semiconductor, the first semiconductor layer being of an n-type; a second semiconductor layer including a nitride semiconductor, the second semiconductor layer being of a p-type; and a light emitting unit provided between the first semiconductor layer and the second semiconductor layer, the light emitting unit including a plurality of barrier layers and a plurality of well layers stacked alternately with the barrier layers, the barrier layers including:
a p-side barrier layer, the p-side barrier layer being second most proximal to the second semiconductor layer among the barrier layers;an n-side barrier layer provided between the p-side barrier layer and the first semiconductor layer; anda first intermediate barrier layer provided between the n-side barrier layer and the p-side barrier layer, the well layers including:
a p-side well layer provided between the p-side barrier layer and the second semiconductor layer, the p-side well layer being in contact with the p-side barrier layer;an n-side well layer provided between the n-side barrier layer and the first intermediate barrier layer, the n-side well layer being in contact with the n-side barrier layer; anda first intermediate well layer provided between the first intermediate barrier layer and the p-side barrier layer, the first intermediate well layer being in contact with the first intermediate barrier layer, first dislocations being more than second dislocations, the first dislocations being included in the first intermediate barrier layer and in an interface between the first intermediate barrier layer and the first intermediate well layer, the second dislocations being included in the p-side barrier layer and in an interface between the p-side barrier layer and the p-side well layer.