Imminent read failure detection using high/low read voltage levels

摘要

Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.

主权项

1. A method for detecting imminent read failures for a non-volatile memory (NVM) system, comprising:
using a normal read voltage level for read operations for an array of non-volatile memory (NVM) cells; adjusting a read voltage level to one or more low voltage levels below the normal read voltage level and for each of the one or more low voltage levels:
performing one or more first read and error correction operations for a plurality of addresses associated with the array of NVM cells; andrecording one or more first addresses for bit errors detected with respect to the one or more first read and error correction operations; adjusting a read voltage level to one or more high voltage levels above the normal read voltage level and for each of the one or more high voltage levels:
performing one or more second read and error correction operations for a plurality of addresses associated with the array of NVM cells; andrecording one or more second addresses for bit errors detected with respect to the one or more second read and error correction operations; comparing the one or more first addresses and the one or more second addresses to determine one or more address matches; and indicating an imminent read failure for the array of NVM cells at least in part based upon the comparison.