Processor memory optimization via page access counting

摘要

To utilize the most efficient memory available to a mobile processor, page access counters may be used to record utilization associated with multiple different memory types. In one embodiment, an operating system routine may analyze the page access counters to determine low utilization pages and high utilization pages to dynamically assign between the multiple different memory types, which may include a more efficient memory type having greater capacity, greater throughput, lower latency, or lower power consumption than a less efficient memory type. As such, in response to detecting a high utilization page in the less efficient memory or a low utilization page in the more efficient memory, contents associated therewith may be copied to the more efficient memory and the less efficient memory, respectively, and virtual-to-physical address mappings may be changed to reflect the reassignment.

主权项

1. A method for efficiently utilizing processor memory, comprising:
monitoring, by a software process executing on a processor, page access counters that measure utilization associated with pages in a main memory located beyond a last-level cache accessible to the processor, wherein the main memory comprises at least a first memory having a first physical memory device type based on a first hardware technology and a second memory having a second physical memory device type based on a second hardware technology, and wherein the first memory has greater efficiency than the second memory; and dynamically changing, by the software process executing on the processor, an assignment associated with at least one of the pages in the main memory between a first physical address space associated with the first memory and a second physical address space associated with the second memory based on the monitored page access counters, wherein dynamically changing the assignment associated with the at least one page comprises: instructing a first memory controller and a second memory controller to switch the assignment associated with the at least one page between the first physical address space and the second physical address space, wherein the first memory controller is directly coupled between the first memory and an interconnection fabric located beyond the last-level cache and wherein the second memory controller is directly coupled between the second memory and the interconnection fabric; and changing a mapping associated with a virtual address that the processor uses to access the at least one page to reflect the switched assignment between the first physical address space and the second physical address space, wherein a memory management unit coupled between the processor and the interconnection fabric maintains the mapping associated with the virtual address in one or more page tables, and wherein the page access counters that measure the utilization associated with the pages in the main memory are integrated into the one or more page tables maintained at the memory management unit; and wherein the first memory comprises a wide input/output (I/O) memory and the second memory comprises a double data rate (DDR) memory.