发明名称 Photonic processor with pattern matching and image recognition
摘要 Apparatus (100) is provided which is arranged to accept an input data stream. In some embodiments, the apparatus (100) comprises a sampler arranged to sample the input data stream to provide k samples thereof, wherein each of the samples is n bits long and a string selector arranged to select m binary strings n bits long from at least a chosen subset of all random binary strings of a predetermined length. The apparatus (100) may further comprise a logical operator arranged to perform a logical function for each of the k samples with each of the selected binary strings to provide a vector, a memory arranged to store a matrix of the vectors generated from k samples, and an address generator arranged to generate RAM address segments from the matrix. In embodiments, the apparatus (100) may comprise a processor for, for example, pattern matching; feature detection, image recognition.
申请公布号 US9330344(B2) 申请公布日期 2016.05.03
申请号 US201013498458 申请日期 2010.09.28
申请人 QINETIQ LIMITED 发明人 Orchard David Arthur;Wilson Rebecca Anne;Pritchard Jonathan Alexander Skoyles;Cooper Martin James;Shepherd Terence John;Lewin Andrew Charles;Tapster Paul Richard;Bennett Charlotte Rachel Helen
分类号 G06F9/00;G05B15/00;G06K9/74;G06F7/02 主分类号 G06F9/00
代理机构 McDonnell Boehnen Hulbert & Berghoff LLP 代理人 McDonnell Boehnen Hulbert & Berghoff LLP
主权项 1. Apparatus arranged to accept a serial input data stream, the apparatus comprising: (i) a sampler arranged to sample the input data stream to provide k samples thereof, wherein each of the samples is n bits long, (ii) a serial to parallel converter arranged to convert the serial input to a parallel signal; (iii) a string selector arranged to select m binary strings n bits long from at least a chosen subset of all random binary strings of a predetermined length, (iv) a logical operator arranged to perform a logical function for each of the k samples with each of the selected binary strings to provide a vector, (v) memory arranged to store a matrix of the vectors generated from k samples, (vi) an address generator, arranged to generate RAM address segments from the matrix wherein the apparatus further comprises an entropy conditioning unit arranged to condition the input stream to ensure that the generated addresses are substantially distributed throughout available address space provided by the RAM.
地址 GB