Power gating circuit and electronic system including the same

摘要

A power gating circuit including a first chain buffer that generates a first sleep signal by buffering an input sleep signal, a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a first switch block including a plurality of first switch cells controlled according to the first sleep signal.

主权项

1. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:
a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit; a first switch block including a plurality of first switch cells controlled by the first sleep signal; a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and a second switch block including a plurality of second switch cells controlled by the second sleep signal, wherein the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element; wherein a number of the plurality of first switch cells is set according to a maximum transition time violation (MTTV) condition for the second sleep signal.