Extensible execution unit interface architecture with multiple decode logic and multiple execution units

摘要

A method and circuit arrangement tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple types of execution units. Among other benefits, when an auxiliary execution unit is coupled to a general purpose processing core with the decode logic for the auxiliary execution unit tightly coupled with the decode logic for the general purpose processing core, the auxiliary execution unit may be used to effectively overlay new functionality for an existing instruction that is normally executed by the general purpose processing core, e.g., to patch a design flaw in the general purpose processing core or to provide improved performance for specialized applications.

主权项

1. A method of executing an instruction in a processing unit, the method comprising:
concurrently forwarding the instruction to first and second decode logic respectively associated with first and second types of execution units, wherein the second decode logic is disposed within a designed, verified and tested core, and wherein the first decode logic is disposed external to the designed, verified and tested core and is interfaced with the second decode logic through an interface; decoding the instruction with the first decode logic; decoding the instruction with the second decode logic; and in response to the first and second decode logic respectively decoding the instruction as a valid instruction for the first and second types of execution units, forwarding the instruction to a first execution unit of the first type of execution unit for execution thereby rather than to a second execution unit of the second type of execution unit based upon the first decode logic having a higher priority than the second decode logic, wherein the second execution unit is disposed within the designed, verified and tested core and wherein the first execution unit is disposed external to the designed, verified and tested core, wherein the designed, verified and tested core, the first decode logic and the first execution unit are disposed in an application specific hardware design, wherein the processing unit includes first and second rename logic respectively associated with the first and second decode logic, wherein the first and second execution units have different register architectures, and wherein the method includes, with the first and second rename logic, applying different renaming operations to the instruction based upon the respective register architectures of the first and second execution units.