Methods and apparatus for adapting pipeline stage latency based on instruction type

摘要

Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.

主权项

1. A method for changing execution latency for performance and power optimization of an instruction class adaptable pipeline processor, the method comprising:
creating, by use of a computer, an application program for the instruction class adaptable pipeline processor, the application program containing class one instructions each executable with a first latency in a class one pipeline and class two instructions each executable with a second latency in a class two pipeline, wherein the first latency is shorter than the second latency; changing an encoding of an original class one instruction of the class one instructions to a second encoded class one instruction that specifies a function of the original class one instruction is to be executed with the second latency to minimize power use while still meeting performance requirements and to create a modified application program; and executing the modified application program on the instruction class adaptable pipeline processor, wherein the second encoded class one instruction is executed and the original class one instruction is not executed.