发明名称 Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness
摘要 Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.
申请公布号 US9330988(B1) 申请公布日期 2016.05.03
申请号 US201414580283 申请日期 2014.12.23
申请人 International Business Machines Corporation 发明人 Adderly Shawn A.;Babinski Kyle;Delibac Daniel A.;DeMuynck David A.;Goddard Shawn R.;Moon Matthew D.;Roma Melissa J.;Schneider Craig E.
分类号 H01L21/66;H01L21/3213 主分类号 H01L21/66
代理机构 Gibb & Riley, LLC 代理人 Gibb & Riley, LLC ;Meyers, Esq. Steven J.
主权项 1. A method comprising: receiving multiple wafers; determining backside roughness levels of said wafers; sorting said wafers into different groups of wafers based on said backside roughness levels; and, manufacturing integrated circuit chips on said wafers, said manufacturing being performed according to integrated circuit chip design and comprising: for each wafer, forming a first layer on a frontside of said wafer;forming a second layer above said first layer;forming openings in said second layer; and,performing an etch process to form openings in said first layer aligned below said openings in said second layer, said etch process being performed differently on said different groups of wafers so as to minimize systematic variations in a width of said openings in said first layer.
地址 Armonk NY US