Semiconductor-on-insulator integrated circuit with reduced off-state capacitance

摘要

An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.

主权项

1. A semiconductor-on-insulator integrated circuit comprising:
a buried insulating layer, wherein the buried insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface; a semiconductor layer having a first surface and a second surface, wherein the first surface of the semiconductor layer contacts the first surface of the buried insulating layer; a handle layer formed over the semiconductor layer; a first transistor formed in the semiconductor layer; a first contact to a first doped region of the first transistor, a second contact to a second doped region source or drain region of the first transistor; a first metal interconnect layer in contact with the second surface of the buried insulating layer, wherein the metal interconnect layer is disposed within the hole in the buried insulating layer and is in contact with the first contact; and a second metal interconnect layer located, at least partially, on an opposite side of the semiconductor layer from the first metal interconnect layer, wherein the second metal interconnect layer is in contact with the second contact; wherein the first and second doped regions are the source and drain regions of a transistor; and wherein a channel of the first transistor lies wholly within an overlapping vertical extent of the source region and the drain region.