Method and system for verifying the design of an integrated circuit having multiple tiers

摘要

A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

主权项

1. A method for verifying a design of an integrated circuit (“IC”) having a plurality of tiers, said method comprising:
conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective plurality of devices; generating a plurality of adjacent tier connections between one of the plurality of devices in respectively different tiers from each other, using a computing device; performing a first resistance-capacitance (“RC”) extraction for each of the plurality of tiers to compute couplings between each of the plurality of devices of the corresponding design layout; and performing a second RC extraction for each of the adjacent tier connections between a pair of adjacent tiers, wherein the second RC extraction step uses a first table to provide capacitive couplings between tiers if the adjacent tiers are face-to-face tiers and a second table to provide capacitive couplings between tiers if the adjacent tiers are a pair of back-to-face tiers.