发明名称 Chip, chip package and die
摘要 In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
申请公布号 US9331059(B2) 申请公布日期 2016.05.03
申请号 US201314101370 申请日期 2013.12.10
申请人 INFINEON TECHNOLOGIES AG 发明人 Allinger Robert;Beer Gottfried;Hoegerl Juergen
分类号 H01L29/10;H01L23/58;H01L25/18;H01L21/66;H01L23/00;G01R31/28;H01L27/02 主分类号 H01L29/10
代理机构 代理人
主权项 1. A chip for a chip package, the chip comprising: a substrate, an integrated circuit over the substrate, the integrated circuit comprising a test circuit and an operation circuit, the test circuit comprising one or more first driver stages each having a first driver performance and the operation circuit comprising one or more second driver stages each having a second driver performance which is different to the first driver performance, first contacts electrically coupled with the one or more first driver stages, and second contacts electrically coupled with the one or more second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode; wherein the first contacts are arranged in a plurality of groups, wherein all first contacts of one group are electrically coupled with each other by a pin that at least partially overlaps all first contacts in the group with the same first driver stage.
地址 Neubiberg DE